1. Field of the Invention
This invention relates to electronic circuits and more specifically to gain stages utilizing operational amplifiers and switched capacitor circuits as resistor equivalents.
2. Description of the Prior Art
FIG. 1 is a schematic diagram of a prior art gain stage utilizing operational amplifier 30 and a switched capacitor resistor equivalent circuit. Switched capacitor resistor equivalents are described, for example, in "Analog Sample Data Filters", IEEE Journal of Solid-State Circuits, August 1972, p. 302. The use of switched capacitor resistor equivalents is particularly desirable in metal oxide silicon (MOS) integrated circuits, in that resistance values and thus, the ratio of resistors, which determines the gain of an operational amplifier stage, are not highly controllable in MOS integrated circuits. However, capacitance ratios are highly controllable in MOS integrated circuits, due to the fact that capacitor areas are controllable, and dielectric thicknesses are relatively uniform across the surface of the semiconductor die. Thus, capacitance ratios, and therefore the gain of operational amplifier circuits utilizing switched capacitor resistor equivalent circuits, are highly controllable in MOS integrated circuits.
The circuit of FIG. 1 comprises operational amplifier 30 having its non-inverting input 18 connected to ground. A switched capacitor resistor equivalent circuit is comprised of MOS switches 12 and 15, and capacitor 14, having capacitance value .alpha.C. This switched capacitor resistor equivalent is connected between input terminal 11 and inverting input lead 17 of operational amplifier 30. MOS switch 15 is connected between capacitor 14 and ground, as shown. Capacitor 20, having capacitance C, is connected between inverting input lead 17 and operational amplifier output 19. Connected in parallel with capacitor 20 is MOS switch 21. MOS switches 12 and 21 are controlled by a first clock, labeled .phi., which is applied to gate terminal 13 of switch 12, and gate terminal 22 of switch 21. MOS switch 15 is controlled by a second clock, .phi., which is the inverse of .phi.. The relationship between .phi. and .phi. is shown in FIG. 2.
During the operation of the prior art gain stage of FIG. 1, the circuit is first initialized by discharging capacitor 20. This is accomplished during the positive half cycle of .phi., which causes switch 21 to close, thereby shorting out capacitor 20. At this time, operational amplifier output 19 is connected to inverting input 17 through switch 21. Thus, the inherent offset voltage for operational amplifier 30, V.sub.off, is present at both output terminal 19 and inverting input lead 17. At the same time, with .phi. high, switch 12 is closed, thereby charging capacitor 14 to a voltage equal to V.sub.in -V.sub.off.
When .phi. goes low, and .phi. goes high, switches 12 and 21 open and switch 15 closes. This connects one side of capacitor 14 to ground through switch 15, causing -(V.sub.in -V.sub.off) to be applied to inverting input lead 17 of operational amplifier 30. The charge conservation equation at inverting input lead 17, is shown by Equation (1). EQU .alpha.C[V.sub.in (NT-T/2)-V.sub.off -(-V.sub.off)]+C[0-(V.sub.out (NT)-V.sub.off)]=0 Equation (1)
where V.sub.in (NT-T/2) equals the input voltage at time NT-T/2, and V.sub.out (NT) equals the output voltage at time NT, where N is a positive integer. Manipulating Equation (1) to obtain an expression for V.sub.out leads to Equation (2). EQU V.sub.out (NT)=.alpha.V.sub.in (NT-T/2)+V.sub.off Equation ( 2)
As can be seen from Equation (2), the inherent voltage offset, V.sub.off, appears in the output voltage V.sub.out. One method of eliminating the effect of V.sub.off in the output voltage is shown in FIG. 3. FIG. 3 is essentially identical to FIG. 1, with the addition of switches 23 and 25. During the initialization period, when .phi. is high, switches 12, 21 and 25 are closed and switches 15 and 23 are open. One plate of capacitor 20 is connected to inverting input lead 17 and output lead 19 (throughput switch 21), and the second plate of capacitor 20 is connected to ground through switch 25. Thus, rather than completely discharging capacitor 20 during the initialization period, capacitor 20 is charged to V.sub.off. During the next half clock cycle when .phi. goes low and .phi. goes high, switches 12, 21, and 25 are open, and switches 15 and 23 are closed. Capacitor 20 is thus connected between inverting input lead 17 and output lead 19. This results in the elimination of the offset voltage component of the output voltage, as shown in Equations (3 ) and (4). EQU .alpha.C[V.sub.in (NT-T/2)-V.sub.off -(-V.sub.off)]+[C(-V.sub.off)-(V.sub.out (NT)-V.sub.off)]=0Equation (3) EQU V.sub.out (NT)=.alpha.V.sub.in (NT-T/2) Equation (4)
The output voltage can be inverted if gate terminal 13 of switch 12 is connected to .phi. rather than .phi., and gate terminal 16 of switch 15 is connected to .phi. rather than .phi.. In a similar manner, switch 15 may be connected to a second input voltage rather than ground, thus providing an output voltage proportional to the difference between the first and second input voltages.
In the absence of ideal switches, an error E.sub.S is introduced reflecting capacitive clock coupling between the gate and drain, and the gate and source, of each MOS switch. This error E.sub.S also includes charge injection which occurs when the MOS switch turns off. The mechanism of this spurious voltage E.sub.S is described in detail in copending U.S. patent application Ser. No. 06/185,356, filed Sept. 8, 1980, and assigned to the assignee of this invention, which is hereby incorporated by reference. Thus, the actual output voltage is shown in Equation (5). EQU V.sub.out (NT)=.alpha.V.sub.in (NT-T/2)+E.sub.S Equation ( 5)
Prior art circuits have been developed which eliminate the inherent offset voltage, V.sub.off, from the output voltage of an operational amplifier switched capacitor resistor equivalent gain stage. See U.S. patent application Ser. No. 06/185,356, filed Sept. 8, 1980 and U.S. patent application Ser. No. 06/079,339, filed Sept. 27, 1979, both of which are assigned to the assignee of this invention. However, prior art circuits have not been able to eliminate the effect of the error term, E.sub.S, caused by parasitic capacitance of MOSFET switches, and charge injection.